1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of electrically conductive features connecting circuit elements in integrated circuits.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are connected by means of electrically conductive features to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase the circuit's functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence increasing the functionality of the circuit, and also reducing signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
As feature sizes in integrated circuits are reduced, sophisticated techniques are required in order to electrically connect the circuit elements of the integrated circuits. If a greater number of circuit elements is formed on the same area, it may be necessary to reduce the dimensions of the electrically conductive features in order to accommodate the electrically conductive features. Additionally, electrically conductive features may be formed in a plurality of levels stacked on top of each other.
In modern integrated circuits, electrically conductive features in higher interconnect levels are frequently made of copper. If, however, copper diffuses into a silicon substrate wherein circuit elements are formed and is incorporated into the crystal lattice of the silicon substrate, deep impurity levels may be created. Such deep impurity levels may lead to a degradation of the performance of circuit elements such as field effect transistors. In order to avoid such problems, electrical connections between circuit elements and the first level of electrically conductive lines are frequently made of tungsten.
A method of forming a semiconductor structure according to the state of the art will be described with reference to FIGS. 1a-1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of a manufacturing method according to the state of the art.
The semiconductor structure 100 comprises a substrate 101. The substrate 101, which may, for example, comprise silicon, comprises a field effect transistor 102. The field effect transistor 102 comprises an active region 103, a source region 108 and a drain region 109. In examples of manufacturing methods according to the state of the art wherein the field effect transistor 102 is an N-type transistor, the material of the substrate 101 may be P-doped and the source region 108 and the drain region 109 may be N-doped. Conversely, in examples of manufacturing methods according to the state of the art wherein the field effect transistor 102 is a P-type transistor, the active region 103 may be N-doped and the source region 108 as well as the drain region 109 may be P-doped. Thus, a PN transition is provided at an interface between the source region 108 and the active region 103 and at an interface between the drain region 109 and the active region 103.
The field effect transistor 102 further comprises a gate electrode 105 flanked by a sidewall spacer structure 107 and separated from the active region 103 by a gate insulation layer 106. A trench isolation structure 104 provides electrical insulation between the field effect transistor 102 and other circuit elements in the semiconductor structure 100. The field effect transistor 102 may be formed by means of methods well known to persons skilled in the art, including advanced techniques of ion implantation, deposition, photolithography, etching, oxidation and annealing.
A layer 110 of a dielectric material is deposited over the substrate 101. The layer 110 may comprise silicon dioxide, silicon nitride and/or silicon oxynitride and may be formed by means of known deposition techniques, such as chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). A thickness of the layer 110 may be greater than a height of the gate electrode 105. After the deposition of the layer 110, a known planarization process, such as chemical mechanical polishing (CMP), may be performed to obtain a planar surface of the layer 110.
Contact vias 111, 112, 113 are formed in the layer 110. To this end, a mask (not shown) covering the layer 110 with the exception of those portions wherein the contact vias 111, 112, 113 are to be formed is formed over the semiconductor structure 100 by means of known methods of photolithography. Thereafter, a known anisotropic etching process, for example, a dry etching process, is performed to remove those portions of the layer 110 which are not covered by the mask. The anisotropy of the etching process may help in obtaining substantially vertical sidewalls of the contact vias 111, 112, 113.
The contact via 111 is formed over the source region 108. Thus, at the bottom of the contact via 111, a portion of the source region 108 is exposed. The contact vias 112, 113 are formed over the gate electrode 105 and the drain region 109, respectively. Hence, the gate electrode 105 is exposed at the bottom of the contact via 112 and the drain region 109 is exposed at the bottom of the contact via 113.
In some examples of manufacturing methods according to the state of the art, an etch stop layer (not shown) comprising a material which is etched at a significantly lower etch rate than the dielectric material of the layer 110 may be provided between the field effect transistor 102 and the layer 110. Thus, the etch process may be reliably stopped as soon as the vias 111, 112, 113 penetrate the layer 110 of dielectric material. After the formation of the contact vias 111, 112, 113, a second etching process may be performed in order to remove portions of the etch stop layer exposed at the bottom of the contact vias 111, 112, 113. After the formation of the contact vias 111, 112, 113, the mask may be removed, for example by means of a known resist strip process.
Subsequently, the contact vias 111, 112, 113 are filled with tungsten. To this end, a first glue layer 114 and a second glue layer 115 are deposited over the semiconductor structure 100. The glue layers 114, 115 may improve adhesion between the tungsten provided in the contact vias 111, 112, 113 and the dielectric material of the layer 110. Additionally, the glue layers 114, 115 may help in obtaining a more favorable crystalline structure of the tungsten if the tungsten is deposited by means of a CVD process and/or a PECVD process.
The first glue layer 114 may comprise titanium and may be formed by means of an ionized metal plasma deposition process. As persons skilled in the art know, ionized metal plasma deposition is a variant of physical vapor deposition wherein metal atoms. which may, for example, be created by sputtering a target comprising the metal to be deposited, are ionized in a plasma. The plasma may be created by means of an electric glow discharge in a carrier gas, which may, for example, comprise nitrogen and/or a noble gas. The electric glow discharge may be created by inductively coupling a radio frequency alternating current to the carrier gas and/or by applying the radio frequency alternating voltage to electrodes provided in the carrier gas. The ionized metal atoms are then accelerated towards the substrate 101 by means of a bias voltage applied between the substrate 101 and an electrode provided with a reactor vessel wherein the ionized metal plasma deposition is performed. The second glue layer 115 may comprise titanium nitride and may be formed by means of a CVD process and/or a PECVD process well known to persons skilled in the art.
A seed layer 116 comprising tungsten is formed over the semiconductor structure 100. The seed layer 116 may be formed by means of an atomic layer deposition (ALD) process. As persons skilled in the art know, ALD is a variant of CVD wherein the semiconductor structure is sequentially exposed to a plurality of gaseous precursor compounds which are sequentially flown to a reactor vessel wherein the semiconductor structure 100 is provided. While a first precursor is flown to the semiconductor structure 100, a substantially monoatomic layer of the first precursor is formed over the second glue layer 115. Since adhesion between molecules of the first precursor may be weak, deposition of more than one monoatomic layer of the first precursor may be substantially avoided by adapting the temperature of the ALD process. Thereafter, a second precursor is flown to the semiconductor structure 100. The second precursor reacts chemically with the first precursor present on the surface of the semiconductor structure 100. In the chemical reaction, tungsten may be created.
After the formation of the seed layer 116, a layer 117 comprising tungsten may be formed over the seed layer 116. To this end, well-known deposition techniques such as CVD and/or PECVD may be employed. In the formation of the layer 117, material deposition in the vicinity of the edges of the contact vias 111, 112, 113 may proceed faster than material deposition in the vicinity of the bottom of the contact vias 111, 112, 113. Therefore, seams 118, 119, 120 may be formed inside the contact vias 111, 112, 113.
Subsequently, a CMP process adapted to remove portions of the glue layers 114, 115, the seed layer 116 and the layer 117 comprising tungsten deposited outside the contact vias 111, 112, 113 may be performed.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. A second layer 121 of a dielectric material is formed over the first layer 110 of dielectric material. In some examples of manufacturing processes according to the state of the art, the second layer 121 may comprise the same material as the first dielectric layer 110. Alternatively, the second layer 121 may comprise a different material than the first dielectric layer 110, for example, a low-k material such as hydrogen silsesquioxane.
In the second layer 121 of dielectric material, trenches 122, 123, 124 are formed. This may be done by means of techniques of photolithography and etching well known to persons skilled in the art.
A barrier layer 125 is formed over the semiconductor structure 100. The barrier layer 125 may comprise tantalum and/or tantalum nitride and may be adapted to prevent a diffusion of copper which will be provided in the trenches 122, 123, 124 into other portions of the semiconductor structure 100.
Subsequently, a seed layer 127 comprising copper is formed over the semiconductor structure 100. This may be done by means of well-known methods such as CVD or PECVD. Thereafter, a layer 126 comprising copper is formed over the seed layer 127, for example, by means of an electroplating process well known to persons skilled in the art. Finally, portions of the seed layer 127 and the layer 206 outside the trenches 122, 123, 124 are removed, for example, by means of a chemical mechanical polishing process.
A problem of the above-described manufacturing process according to the state of the art is that tungsten, which is used for filling the contact vias 111, 112, 113, has a relatively high resistivity. Thus, as the size of the contact vias 111, 112, 113, in particular a diameter thereof, is reduced, electrical currents flowing through the contact vias 111, 112, 113 may be subject to a high resistance, which may lead to an increase of signal propagation delays as well as to an undesirable creation of heat. The electric resistance of the contact vias 111, 112, 113 filled with tungsten may further be increased by the presence of the seams 118, 119, 120. Additionally, the glue layers 114, 115 may have an even higher resistivity than tungsten. Thus, the presence of the glue layers 114, 115 may further contribute to the increase of the electrical resistance of the contact vias 111, 112, 113.
A further problem of the above-described manufacturing process according to the state of the art is that it may occur that one or more of the seams 118, 119, 120 are opened during the CMP process which is performed to remove portions of the glue layers 114, 115, the seed layer 116 and the layer 117 outside the contact vias 111, 112, 113. This may lead to a significant reduction of the electrical conductivity of the contact vias 111, 112, 113 filled with tungsten or even to a failure of the semiconductor structure 100.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.